Fix COND_FMS foldings with corrected negation and masking.
Corrects issues in folding conditional fused multiply-subtract operations, improving optimization accuracy.
This commit addresses errors in GCC’s middle-end optimization pass related to folding conditional fused multiply-subtract (COND_FMS) operations. Typos in the optimization patterns led to incorrect negation of values and missing masks, impacting the accuracy of FMA (Fused Multiply-Add) optimizations. The fix corrects these pattern errors and adds new test cases to ensure robustness, particularly for SVE (Scalable Vector Extension) on AArch64 architectures.
In Details
This patch corrects two specific issues within the match.pd patterns responsible for folding COND_FMS operations. The first problem was a failure to negate the 'else' value in certain conditional FMS transformations. The second was a missing mask in one of the patterns. These errors could lead to incorrect intermediate representation generation, preventing FMA forwarding or causing incorrect results. The commit provides corrected patterns and adds several new test cases for AArch64 SVE to cover COND_FMA, COND_FMS, COND_FNMA, and COND_FNMS with various conditions and operands, reso…
- middle-end
- Refers to the optimization phases of a compiler that operate on an intermediate representation (like GIMPLE) after parsing and before target-specific code generation.
- COND_FMS
- A Conditional Fused Multiply-Subtract operation. It performs a multiply and subtract, but the result is conditionally applied based on a condition, often related to vector operations.
- folding
- An optimization technique where constant expressions or predictable operations are evaluated at compile time rather than runtime.
- FMA
- Fused Multiply-Add. A single instruction that performs both a multiplication and an addition (or subtraction), often with higher precision and performance than separate operations.
- AArch64
- The 64-bit execution state of the ARM architecture, commonly used in mobile devices, servers, and laptops. GCC supports this architecture.
- SVE
- Scalable Vector Extension. An Advanced SIMD (Single Instruction, Multiple Data) instruction set for ARM processors that allows vector registers to be of a variable length, adapting to the hardware.