Support ACEv1 bsr instructions
Adds support for ACEv1 Block Scale Register (BSR) instructions, using specific naming conventions for future extensibility.
This commit introduces support for ACEv1 BSR instructions, implementing specific naming conventions like bsr0 and using insert/extract in intrinsic names to align with existing load/store conventions. It also uses the term ‘full’ for bsrmovf to clarify it refers to the entire data, not floating-point. Changes span intrinsic headers, builtin definitions, and machine-specific instruction patterns, with new test cases added.
In Details
Adds ACEv1 BSR (Block Scale Register) instructions, including bsrinit, bsrmovh_load, bsrmovl_load, bsrmovh_store, bsrmovl_store, and bsrmovf. Intrinsics use names like bsr0_init, bsr_movh_load to reserve space for future BSR extensions and clarify intent. ix86_expand_builtin is updated to handle these new builtins. Machine description (sse.md) adds corresponding UNSPEC patterns. Test suite includes specific tests for these BSR instructions.
- ACEv1
- AI Compute Extensions version 1, a new x86 instruction set architecture designed for AI and compute-intensive workloads.
- BSR
- Block Scale Register, a component of the ACEv1 ISA likely used for scaling or related operations.
- intrinsics
- Special functions that allow C/C++ code to directly invoke specific machine instructions, often providing performance benefits over traditional function calls.