RISC-V: Add intrinsic support for Zvabd vector extension.
Adds intrinsic support for the RISC-V Zvabd vector extension, fixing an ICE and improving intrinsic generation.
This commit introduces intrinsic support for the RISC-V Zvabd (Vector Absolute Difference) extension. It resolves an ICE (Internal Compiler Error) that occurred during intrinsic emission by adopting a vwmacc-like pattern. This change ensures correct intrinsic generation and better reflects the Zvabd extension’s semantics.
In Details
The RISC-V vector extension Zvabd involves operations where operand 0 and operand 2 could differ, leading to an ICE with the previous VWABAD machine description pattern due to constraint mismatches (+ vs 0). This change revises the pattern to be vwmacc-like, resolving the ICE and handling operand constraints correctly, including DOUBLE_TRUNC_SIGNED types via genrvv-type-indexer.cc. It also correctly tags required extensions and uses new overlap constraints.
- Zvabd
- A RISC-V vector extension that provides instructions for calculating the absolute difference of vector elements.
- ICE
- Internal Compiler Error. An unrecoverable error that occurs within the compiler itself during the compilation process, indicating a bug in the compiler.
- intrinsic
- A function that performs a specific operation, often in assembly language, and is directly supported by the compiler. Intrinsic functions provide a way to access hardware-specific features or perform low-level operations efficiently.
- vwmacc
- A type of vector multiply-accumulate instruction, commonly found in vector processing units. It multiplies elements of two vectors and adds the result to corresponding elements of a third vector.
- SEW
- Single-Element Width. In RISC-V vector processing, SEW defines the bit-width of individual elements within a vector register.