arm: Handle Neon vec_dup from select of 128-bit vector
Improves Neon `vec_dup` handling for 128-bit vectors, allowing core registers as sources.
This commit enhances the ARM Neon backend’s handling of vec_dup operations on 128-bit vectors. It allows core registers to be used as source operands without needing to copy the entire vector to VFP/SIMD registers. The implementation now efficiently extracts the required lane to the lower bits of a scratch core register, or uses the core register directly if no shift is needed, simplifying code generation and potentially improving performance.
In Details
This patch refactors patterns in config/arm/neon.md to improve the handling of vdup operations for 128-bit Neon vectors. Specifically, it addresses the lack of a direct vdup from a lane in a 128-bit vector by enabling the use of core registers as source operands. The implementation splits the input vector, allowing extraction of the appropriate lane to a scratch core register, or direct use if no shift is required. New patterns neon_vdup_lane<VQ2BF:mode>_internal are introduced, and existing ones are updated for clarity by disambiguating names with iterator suffixes.
- Neon
- An advanced SIMD (Single Instruction, Multiple Data) instruction set extension for ARM processors, designed to accelerate multimedia and signal processing tasks by operating on multiple data elements in parallel.
- vec_dup
- A Neon intrinsic function that duplicates a scalar value or a vector lane into all lanes of a vector. This is used for initializing vectors with constant data.
- 128-bit vector
- A data type that holds 128 bits of information, typically processed in parallel by SIMD instructions. In Neon, this can hold multiple smaller data types like 16 8-bit integers or 4 32-bit floats.
- core register
- A general-purpose register within the main CPU core, as opposed to specialized registers like those for floating-point or SIMD operations.
- VFP register
- A register associated with the Vector Floating-Point unit, used for floating-point calculations.