RISC-V: Add test cases for vector multiply-accumulate instructions.
Adds test cases for vwmacc and vwmaccu vector instructions on RISC-V, covering register overlap and other scenarios.
New test cases have been added for the RISC-V vector multiply-accumulate instructions, specifically vwmacc.vv and vwmaccu.vv. These tests cover scenarios including register group overlap, ensuring correct behavior for signed and unsigned operations across various data types and modes. Additionally, specific checks are included for the ‘csrr not asm’ condition when overlap is enabled.
In Details
RISC-V vector extension tests are expanded. Commit 2be327c50de607ab0d8c1a2295160313c7edf6db relaxes the register constraints for vwmacc[u].vv instructions in the vector-md, allowing for register group overlap similar to other vv-type instructions. The subsequent commits (c5d147d7370fb36834c9348c5d3bab229d89fb3e, 4f75092d25c099363892d03cb50b1142fb20bdcc, 55afdf36b7a2acd881c93485ce2af6d1cf006e18) introduce comprehensive test suites in gcc/testsuite/ to validate these instructions, including tests for specific overlap conditions and the 'csrr not asm' check.
- vwmacc.vv
- A RISC-V vector instruction for a 2x16-bit to 32-bit multiply-accumulate operation, operating on vector registers.
- vwmaccu.vv
- A RISC-V vector instruction for a 2x16-bit to 32-bit unsigned multiply-accumulate operation, operating on vector registers.
- RISC-V Vector Extension (RVV)
- A set of instructions for the RISC-V architecture that enable efficient processing of vector and matrix data, crucial for high-performance computing and scientific applications.
- register group overlap
- A condition in RISC-V vector operations where the destination register group for an instruction might overlap with the source register group, requiring careful handling by the compiler and hardware.