RISC-V: Spill more unsplittable moves.
RISC-V compiler improves handling of complex data moves, reducing spills.
This patch enhances the RISC-V compiler’s ability to handle complex data movements, particularly ‘unsplittable’ moves involving arbitrary data modes. It extends the riscv_subpart function to manage sub-parts of any mode and uses this capability to move spilled TFmode values in word-sized chunks. This change addresses issues with quadword splits and int128 data types, reducing the occurrence of spills in such scenarios.
In Details
The riscv_subpart function in the RISC-V backend is extended to handle sub-parts of arbitrary machine modes, not just fixed sizes. This improved functionality is then used in spill_subreg_move and riscv_split_quadword_move to correctly handle complex moves, such as those involving TFmode (quadword floating-point) or int128 types, by breaking them into word-sized chunks. This directly addresses PRs related to spilling in these scenarios.
- RISC-V
- An open-standard instruction set architecture (ISA) based on Reduced Instruction Set Computing principles. It is designed to be simple, modular, and extensible.
- spill
- In compiler optimization, a spill occurs when the compiler needs to store a temporary value from a register into memory because there are no available registers for subsequent operations.
- TFmode
- A GCC internal machine mode representing a 128-bit floating-point number (often
__float128). - quadword
- A unit of data consisting of 64 bits (8 bytes).
- subreg
- A part of a machine register. Compilers often use subregs to access smaller parts of larger registers, especially in architectures with complex register usage.