Set REGMODE_NATURAL_SIZE for advsimd vectors on AArch64
AArch64 now correctly sets REGMODE_NATURAL_SIZE for advsimd vectors, ensuring subregister validity for vector components.
This change sets the REGMODE_NATURAL_SIZE for AArch64’s advsimd vectors to the size of a single vector element. This aligns with recent RISC-V changes and ensures that subregisters representing parts of a vector are correctly identified as invalid if they are smaller than a full vector, preventing incorrect code generation.
In Details
AArch64's aarch64_regmode_natural_size function is updated to return the size of one advsimd vector element. This change ensures that the compiler correctly interprets the natural size of vector register modes. Consequently, any attempt to form a subregister that is smaller than a full vector will be considered invalid, mirroring similar adjustments made for RISC-V and preventing potential ICEs or incorrect code generation related to vector subregister manipulation.
- REGMODE_NATURAL_SIZE
- A GCC internal macro or function that returns the natural byte size of a given machine register mode. This is crucial for correctly handling subregisters and type sizes.
- advsimd
- An AArch64 specific SIMD (Single Instruction, Multiple Data) instruction set extension, often used for multimedia and signal processing tasks.
- subreg
- A smaller part of a larger register, exposed as a distinct register by the compiler for operations on subsets of data. For example, the lower 32 bits of a 64-bit register can be a subregister.
- AArch64
- The 64-bit ARM architecture.
- RISC-V
- An open-source instruction set architecture (ISA) that is modular and extensible.