Add test cases for vwmaccsu.vv reg overlap.
New test cases enhance RISC-V vector testing by focusing on register overlap for vwmaccsu.vv.
This commit introduces a comprehensive set of test cases for the RISC-V Vector extension, specifically targeting the vwmaccsu.vv instruction concerning register group overlap. These tests aim to ensure correct behavior when vector registers are reused or overlap during the execution of this instruction, covering various data types and vector lengths.
In Details
This commit adds numerous test cases to gcc.target/riscv/rvv/autovec/group_overlap/ for the vwmaccsu.vv instruction. These tests cover different data types (i8, i16, i32) and mask/element counts (m1, m2, m4, mf2, mf4, mf8), focusing on scenarios where vector registers might overlap. A new test helper macro is introduced in group_overlap.h.
- RISC-V
- An open-standard instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles.
- RVV
- RISC-V Vector extension. An extension to the RISC-V ISA that provides support for single instruction, multiple data (SIMD) vector processing.
- vwmaccsu.vv
- A RISC-V Vector instruction for Multiply-Accumulate Signed-Unsigned, Vector-Vector. It performs a signed multiply on two source vectors, adds the result to a third vector, and stores it in a destination vector. The 'su' indicates signed source 1 and unsigned source 2.
- register overlap
- A situation in vector processing where different operations might use the same physical registers, potentially leading to data dependencies or requiring careful management of register lifetimes.