i386: Correct SSE vector concat patterns for SSE4.1
i386: Fixes incorrect conditions for SSE vec_concatv2{sf,si} patterns when SSE4.1 is enabled.
This commit corrects instruction selection for SSE vector concatenation on x86. It fixes an incorrect condition in vec_concatv2sf and vec_concatv2si patterns, preventing them from being selected when SSE4.1 is available and the operands are not compatible with the SSE4.1 specific instructions. Additionally, the generic SSE patterns are now disabled when SSE4.1 is enabled to ensure the more appropriate SSE4.1 patterns are used.
In Details
The vec_concatv2sf and vec_concatv2si patterns in the i386 backend's SSE instruction set were incorrectly advertising availability. Specifically, the SSE4.1 versions of these patterns accept a memory operand 1 only when operand 2 is CONST0_RTX. The old condition was too permissive, allowing cases where operand 1 was MEM and operand 2 was a non-zero register, which is not encodable. This change restricts the condition for these SSE4.1 patterns to match the operand constraints more accurately. Furthermore, the generic SSE patterns (*vec_concatv2sf_sse, *vec_concatv2si_sse) are now d…
- i386
- The architectural family name for Intel's 32-bit and 64-bit x86 processors. GCC uses this name for its backend targeting these CPUs.
- SSE
- Streaming SIMD Extensions. A set of SIMD (Single Instruction, Multiple Data) instructions for x86 processors that allow performing the same operation on multiple data points simultaneously.
- SSE4.1
- A specific revision of the SSE instruction set, introducing new instructions and capabilities beyond earlier SSE versions.
- insn condition
- A predicate within GCC's machine description files that determines whether a particular instruction pattern can be used for a given set of operands.
- pattern
- In GCC's backend code, a pattern defines a machine instruction or a sequence of instructions, specifying the operands and how they map to the target's instruction set.
- RTL
- Register Transfer Language, an intermediate representation used by GCC. It describes operations at a lower level than GENERIC, closer to machine code, and is heavily manipulated by optimization passes.
- MEM
- Represents a memory operand in GCC's RTL representation.
- CONST0_RTX
- A constant zero value represented in GCC's RTL.