aarch64: Add SVE AES2 ACLE builtins.
New ARM SVE AES2 builtins and instructions are now supported for AArch64.
GCC now supports Advanced SIMD and Floating-point (ACLE) extensions for AArch64, specifically for the SVE AES2 features. This includes adding built-in functions and RTL patterns for multi-vector AES indexed instructions and 128-bit PMULL/PMLAL pairs. Corresponding feature macros for SVE AES2 and SSVE AES have also been defined.
In Details
This commit adds support for SVE AES2 ACLE builtins on AArch64, including svaese_lane, svaesd_lane, svaesemc_lane, svaesdimc_lane, svpmull_pair, and svpmlal_pair. New unspec (UNSPEC_SSVE_LANE_SELECT), function expanders, and RTL patterns are introduced. Preprocessor feature macros __ARM_FEATURE_SVE_AES2 and __ARM_FEATURE_SSVE_AES are defined, and tests are updated.
- aarch64
- The 64-bit ARM architecture, commonly used in mobile devices, servers, and embedded systems.
- SVE (Scalable Vector Extension)
- An ARM architecture extension that provides flexible vector processing capabilities, allowing vector lengths to adapt to hardware.
- ACLE (ARM C Language Extension)
- A set of compiler intrinsics and extensions for ARM C and C++ compilers, providing access to specific ARM instructions and features.
- AES
- Advanced Encryption Standard, a widely used symmetric encryption algorithm.
- PMULL/PMLAL
- ARM assembly instructions for polynomial multiplication and multiply-accumulate operations, often used in cryptography.
- Builtin functions
- Functions provided by the compiler that map directly to specific hardware instructions or optimization patterns, often prefixed with
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