RISC-V: Add test cases for vwredsum.vs register overlap
Adds tests to ensure no register overlap for RISC-V vwredsum.vs.
This commit introduces new test cases to verify that the vs1 register in the RISC-V vwredsum.vs instruction does not overlap with the vs2 register group. This helps prevent incorrect register usage and ensures the correct interpretation of operands.
In Details
These commits add test cases for register group overlap in RISC-V vector extension instructions, specifically vwredsum.vs and vwredsumu.vs. The tests target scenarios where the vs1 operand might incorrectly fall within the vs2 register group, which is forbidden by the RISC-V vector specification (Section 5.2). The fix involves adding a new constraint (Wn3) and associated logic in riscv-v.cc to prevent such overlaps during instruction selection.
- RISC-V vector extension
- An extension to the RISC-V instruction set architecture that adds support for single instruction, multiple data (SIMD) operations, allowing a single instruction to process multiple data elements in parallel.
- vwredsum.vs
- RISC-V vector instruction for widening signed integer reduction (summation).
.vsindicates that the destination register group is specified by thevdregister and the source register groups arevs1andvs2. - SEW
- Standard Element Width. Refers to the width of individual data elements within a vector register (e.g., 8-bit, 16-bit, 32-bit).
- EEW
- Effective Element Width. The width of the elements being processed by a vector operation, which can be different from the SEW, especially in widening operations.
- Register group
- A contiguous block of vector registers used by a single instruction. The size of the group depends on the operation's element width and the vector length.