RISC-V: Fix subword address computation for big-endian targets
Ensures correct sub-word atomic operations on big-endian RISC-V by fixing address calculation.
A fix has been implemented for the riscv_subword_address function to correctly compute sub-word addresses for built-in atomic operations on big-endian RISC-V targets. This resolves failures in multiple libatomic and target-specific tests that were caused by incorrect address generation.
In Details
The riscv_subword_address function in the RISC-V backend now includes an emit_move_insn for big-endian targets. This ensures that sub-word addresses for atomic operations, such as those used in libatomic, are computed correctly, preventing issues that arise from the byte-addressing discrepancies between big-endian and little-endian representations when accessing smaller data types within larger memory locations.
- sub-word address
- The memory address of a data element that is smaller than the processor's native word size (e.g., a byte or a half-word within a larger integer).
- big-endian
- A byte order where the most significant byte is stored at the lowest memory address. This contrasts with little-endian, where the least significant byte is at the lowest address.
- atomic operations
- Memory operations that are guaranteed to execute indivisibly, meaning they appear to occur instantaneously from the perspective of other threads or processors. This is crucial for maintaining data integrity in concurrent programming.
- libatomic
- A GCC library that provides atomic built-in functions, enabling thread-safe memory operations that are indivisible and appear to complete in a single, uninterruptible step.