Use hard-register constraints in AVR target fixed-point instructions
Improves AVR code generation for fixed-point operations by using hard-register constraints.
This commit refactors the AVR target’s fixed-point instruction definitions to utilize hard-register constraints. This change aims to improve code generation efficiency and correctness for fixed-point arithmetic, particularly for multiply operations, by better aligning with the architecture’s register allocation.
In Details
The gcc/config/avr/avr-fixed.md file is updated to replace explicit hard register usage in its instruction patterns and expanders with hard-register constraints. The muluqq3_nomul expander remains an exception as it relies on the combine pass, which currently has limitations with hard-register constraints. This modification targets PR target/121343, aiming for more robust register allocation.
- hard-register constraints
- In GCC's machine description files, a constraint that specifies a particular physical register must be used for an operand.
- fixed-point arithmetic
- Arithmetic operations on numbers that have a fixed number of digits after the decimal point, often used when floating-point hardware is unavailable or for specific financial calculations.
- insns and expanders
- In GCC's machine description files, 'insns' define machine instructions, and 'expanders' define how higher-level operations are translated into sequences of these machine instructions.