rs6000: Optimize TLS access with combine patterns
Reduces Thread Local Storage access instructions from three to two on rs6000.
This commit optimizes Thread Local Storage (TLS) variable access on the rs6000 architecture by introducing new ‘combine’ patterns in the instruction scheduler. These patterns merge the address calculation and the load operation into a single instruction sequence, reducing the overhead from three instructions down to two and improving performance.
In Details
This patch enhances the rs6000 backend by adding new combine patterns to the instruction selection for Thread Local Storage (TLS) access. Specifically, it merges the addis instruction (for the high part of the offset) and the subsequent addi (for the low part) with the lwz load instruction. This optimization reduces the instruction count for TPreload operations from three to two, streamlining access to TLS variables.
- rs6000
- The codename for IBM's PowerPC architecture, commonly used in servers and workstations. GCC has a backend for this architecture.
- TLS
- Thread Local Storage. A mechanism that provides each thread with its own copy of a variable, ensuring data isolation between threads.
- combine patterns
- In compiler instruction scheduling, a technique to recognize and combine multiple simple instructions into a single, more complex instruction or instruction sequence.
- TPreload
- A specific type of Thread Local Storage access common on PowerPC architectures, involving a two-instruction sequence to calculate the address of a TLS variable.
- lwz
- Load Word and Zero. A PowerPC assembly instruction to load a 32-bit word from memory into a general-purpose register, zero-extending the result.
- addis
- Add Immediate Shifted. A PowerPC assembly instruction that adds an immediate value, shifted left by 16 bits, to a register.
- addi
- Add Immediate. A PowerPC assembly instruction that adds an immediate value to a register.