Fix RISC-V ADDI+AND+CTZ optimization bugs
Corrects two flaws in an optimization that transforms sequences of ADDI, AND, and CTZ instructions on RISC-V.
This commit addresses two bugs in a RISC-V optimization that converts sequences of ADDI, AND, and CTZ (count trailing zeros) instructions into a more efficient CTZ followed by BCLR (bit clear). The first bug caused the original AND instruction to be incorrectly retained, leading to the clearing of two bits instead of one. The second bug was an off-by-one error in the safety check for moving the CTZ instruction, which could lead to incorrect transformations when the AND instruction modified a value used by CTZ. Both issues are now fixed, and a new test case is added.
In Details
Fixes two bugs in the ADDI+AND+CTZ -> CTZ+BCLR optimization for RISC-V, as reported in PR target/127306. The first bug involved incorrectly leaving the original AND instruction when CTZ was found after it, causing double bit clearing. The second was an off-by-one error in find_later_ctz's scan logic, which failed to detect when the AND instruction modified the CTZ input. The fix removes the extraneous AND and corrects the scan logic.
- ADDI
- Add Immediate, a RISC-V instruction that adds an immediate value to a register.
- AND
- Bitwise AND operation, often implemented as an instruction.
- CTZ
- Count Trailing Zeros, an instruction that counts the number of zero bits starting from the least significant bit.
- BCLR
- Bit Clear, an instruction that clears a specific bit in a register. In this context, it's used to clear the lowest set bit.
- RISC-V
- An open standard instruction set architecture (ISA) based on Reduced Instruction Set Computing principles.
- optimization
- A compiler transformation that aims to improve the performance or reduce the size of the generated code.
- RTL
- Register Transfer Level, an intermediate representation used in GCC after the high-level language is parsed and transformed.