RISC-V: Consider spills in conv-dynamic LMUL for vector operations.
RISC-V vector code generation now considers spills when determining LMUL for conv-dynamic mode.
The RISC-V vector code generation, specifically for the -mrvv-max-lmul=conv-dynamic option, now accounts for potential data spills. Previously, this mode solely relied on the size ratio of the largest and smallest types, sometimes leading to unexpected spills in applications like x264. This change integrates spill estimation into the ‘conv-dynamic’ mode and refactors related logic for clarity.
In Details
The RISC-V vector cost model's estimate_lmul logic for conv-dynamic now incorporates spill analysis. Previously, conv-dynamic only considered type size ratios. This commit merges spill estimation from dynamic mode into conv-dynamic and refactors the LMUL decision-making code, including extracting comparison logic into compare_lmul_to and computing type size ratios earlier in add_stmt_cost.
- RISC-V
- An open-standard instruction set architecture (ISA) based on Reduced Instruction Set Computing principles. It is designed to be simple, modular, and extensible.
- LMUL
- In RISC-V vector operations, 'LMUL' (or 'L-length multiplier') specifies the number of vector registers to be used for a vector operation. A higher LMUL allows operations on larger vectors but may consume more register resources.
- conv-dynamic
- A RISC-V vector compilation option where the optimal LMUL is determined dynamically based on type sizes and, now, spill awareness.
- spill
- In compiler optimization, a spill occurs when the compiler needs to store a temporary value from a register into memory because there are no available registers for subsequent operations.
- vector operations
- Computational operations that process multiple data elements in parallel using specialized vector instructions, common in high-performance computing and multimedia processing.