RISC-V: Add test cases for widening insn ICE
Added test cases to the RISC-V backend to catch an ICE with widening instructions.
This commit adds several test cases to the RISC-V backend’s test suite to address an Internal Compiler Error (ICE). The ICE occurs when a widening instruction is encountered where the destination register’s number of registers (nregs) is less than that of the source register. These new tests specifically target this scenario to ensure the compiler handles such cases correctly and avoids crashing.
In Details
The RISC-V Vector (RVV) extension uses widening instructions that operate on vector registers. An ICE was observed in the backend when attempting to process a widening instruction where the destination vector register had fewer elements (nregs) than the source vector register. This indicates a mismatch in expected vector lengths or register allocation. The added test cases in gcc.target/riscv/rvv/base/ directly trigger this condition to verify the fix.
- RISC-V
- An open-standard instruction set architecture (ISA) based on Reduced Instruction Set Computing principles.
- RVV
- RISC-V Vector extension, which provides instructions for SIMD-like vector processing.
- widening instruction
- An instruction that operates on data of a certain size and produces a result of a larger size, often used in vector processing to increase data throughput.
- ICE
- Internal Compiler Error, an unrecoverable error within the compiler itself, usually indicating a bug.
- nregs
- Number of registers, in the context of RISC-V vectors, this likely refers to the number of elements within a vector register or the number of vector registers involved in an operation.