Arc: Fix invalid register index addressing for uncached stores
GCC's Arc backend now correctly handles register-based addressing for uncached stores, fixing invalid operand issues.
A bug in GCC’s Arc backend that allowed invalid register-index addressing for uncached stores has been fixed. The stdi<mode> instruction incorrectly used a too-liberal predicate, allowing [reg,reg] operands which are not valid on Arc. This commit corrects the addressing mode by forcing the address into a register when necessary and uses a more restrictive predicate for the destination operand.
In Details
This commit addresses PR126157 by modifying Arc's prepare_move_operands and machine description. The issue stemmed from -ffuse-ops-with-volatile-access which enabled (plus (reg) (reg)) as a destination operand for stdi<mode>, an invalid format. The fix involves using move_dest_operand and non_mod_move_dest_operand predicates, the latter specifically disallowing PRE/POST increment/decrement, to ensure the address is a valid register or memory location for uncached stores.
- Arc
- A family of 32-bit RISC microprocessors developed by Synopsys, often used in embedded systems.
- uncached store
- A memory write operation that bypasses the CPU's cache, writing directly to main memory. This is often used for memory-mapped I/O or specific hardware interactions.
- register index addressing
- A memory addressing mode where the base address is in one register and an offset or second index is in another register.
- predicate
- In the context of GCC's machine description, a predicate is a condition used to determine if a particular instruction pattern is valid or can be generated for a given target.
- POST_INC
- A type of addressing mode where the operand register is incremented after its value is used as the memory address.