RISC-V: Improve conditional zero optimization with Zicond extension
Optimizes conditional zero operations for RISC-V by mapping greater-than comparisons to less-than-or-equal and using the Zicond extension.
This change enhances RISC-V optimization by improving how conditional zeroes are generated for comparisons against immediate values. It introduces new split patterns and maps greater-than conditions to less-than-or-equal, allowing them to be efficiently handled by the Zicond extension. This results in replacing redundant immediate loads with instructions like slti or sltiu followed by czero.nez or czero.eqz, producing more compact and efficient code.
In Details
This commit refactors conditional zero optimization for the RISC-V Zicond extension by introducing define_split patterns in zicond.md. It adds a gt_to_le code attribute to map sgt and sgtu operations to their sle and sleu equivalents, enabling the use of the sle_operand predicate. This allows previously unoptimized if_then_else constructs involving conditional zeroing based on greater-than comparisons to be split into slti or sltiu followed by czero.nez or czero.eqz instructions, addressing PR target/127374.
- Zicond
- A RISC-V extension that provides additional conditional operations, including instructions for conditional zeroing.
- define_split
- A macro used in GCC's target-specific configuration files (e.g.,
.mdfiles) to define how a complex instruction or operation can be broken down into simpler ones. - sgt
- Set Greater Than. A RISC-V instruction that sets a destination register based on whether the source operand is greater than another source operand.
- slti
- Set Less Than Immediate. A RISC-V instruction that sets a destination register based on whether a source register is less than an immediate value.
- czero.nez
- Conditional Zero, Not Equal Zero. A RISC-V Zicond instruction that conditionally zeroes a destination register based on the result of a comparison.