FRIDAY, AUGUST 14, 2026
risc-v
Add more test cases for vwmaccsu.vv.
New test cases improve coverage for the RISC-V vwmaccsu.vv instruction, particularly concerning register overlap.
This commit expands the test suite for the RISC-V vector instruction vwmaccsu.vv. Additional test cases have been added to specifically cover scenarios involving register overlap and the csrr instruction when overlap is enabled, ensuring more robust validation of this vector operation.
In Details
This commit adds new test cases to gcc.target/riscv/rvv/base/pr112431-51.c. These tests aim to improve coverage for the vwmaccsu.vv instruction, focusing on the interaction with csrr when register overlap is enabled in the RISC-V Vector extension.
For Context
- RISC-V
- An open-standard instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles.
- RVV
- RISC-V Vector extension. An extension to the RISC-V ISA that provides support for single instruction, multiple data (SIMD) vector processing.
- vwmaccsu.vv
- A RISC-V Vector instruction for Multiply-Accumulate Signed-Unsigned, Vector-Vector. It performs a signed multiply on two source vectors, adds the result to a third vector, and stores it in a destination vector. The 'su' indicates signed source 1 and unsigned source 2.
- intrinsic
- A function provided by a compiler that corresponds directly to a specific machine instruction or a small sequence of machine instructions. Intrinsics provide a way to access hardware capabilities from high-level code.