WEDNESDAY, SEPTEMBER 2, 2026
risc-v
RISC-V: Allow register overlap for vwmaccu.vx undef instruction
RISC-V vector extension now allows register overlap for the `vwmaccu.vx` undef instruction.
This commit enables register overlap for the ‘undef’ form of the vwmaccu.vx dual-widen ternary VX instruction in the RISC-V vector extension. This change aligns the vwmaccu.vx instruction’s register handling with other similar instructions, ensuring consistency.
In Details
The undef form of vwmaccu.vx is generated by combining vec_duplicate and vwmaccu.vv. This commit modifies the vector instruction pattern matching in config/riscv/vector.md to use the Wvr constraint, permitting register overlap for this instruction similar to other dual-widen ternary VX instructions.
For Context
- vwmaccu.vx
- A RISC-V vector instruction for fused multiply-accumulate operations with unsigned elements, operating on two source vectors and producing a result vector. The 'undef' form implies a specific generation path.
- register overlap
- A situation where different instructions or parts of instructions use the same physical registers, requiring careful management by the compiler and processor to avoid data corruption or incorrect execution.
- VX instruction
- A type of RISC-V vector instruction that takes a scalar value as one of its operands.
- Wvr constraint
- A constraint used in GCC's machine description files (like vector.md) to specify register operand requirements. 'Wvr' likely indicates a requirement for a vector register that supports wider operations.