RISC-V: Add reassociation width hook for tuning
RISC-V tune parameters now specify reassociation widths for integer, float, and vector operations.
This commit introduces the riscv_reassociation_width function and defines TARGET_SCHED_REASSOCIATION_WIDTH to allow per-tune reassociation widths for RISC-V targets. Specific tunes like ‘generic-ooo’ and ‘xt-c9501fdvt’ receive wider widths (2/2/1 and 3/2/1 respectively) for integer, floating-point, and vector operations, while others default to a width of one. This aims to improve instruction scheduling and performance by allowing more flexible instruction reordering.
In Details
The TARGET_SCHED_REASSOCIATION_WIDTH hook is now implemented for RISC-V. This hook informs the instruction scheduler about how many operations of a certain type (integer, float, vector) can be reassociated to improve instruction-level parallelism. Previously, all RISC-V tunes used a default width of one. This change introduces per-tune specific widths, configuring 'generic-ooo' and 'xt-c9501fdvt' with wider reassociation capabilities to better match their microarchitectural features.