RISC-V vector crypto register allocation fixed.
Prevents register overlap issues in RISC-V vector crypto instructions.
This commit addresses register allocation conflicts for RISC-V vector crypto instructions, specifically for vsm3me.vv, vsm3c.vi, vaes*.vs, vsm4r.vs, vsha2ms.vv, vsha2ch.vv, and vsha2cl.vv. It introduces early-clobber destination constraints to prevent the destination register (vd) from overlapping with source registers (vs2 or vs1) where specified by the Vector Crypto extension.
In Details
RISC-V vector crypto instructions have specific register encoding constraints where vd may overlap with vs2 or vs1. This commit modifies the machine description (vector-crypto.md) to use early-clobber constraints for patterns like vsm3me.vv and vaes*.vs, resolving conflicts identified in PR126196. Overlaps are preserved for instructions not subject to these stricter reservations.
- vd
- The destination vector register in RISC-V vector instructions.
- vs1
- The first source vector register in RISC-V vector instructions.
- vs2
- The second source vector register in RISC-V vector instructions.
- early-clobber
- A constraint in instruction patterns indicating that a destination register is written before it is read, or that it overlaps with a source register in a way that requires special handling to avoid data corruption.
- RISC-V Vector Crypto
- An extension to the RISC-V vector architecture that provides specialized instructions for cryptographic operations.