GCC Newspaper
OCTOBER 6, 2026
Date
/
Architectures
Components
Topics
News & Policy
Other
risc-v

RISC-V: Fix ICE for widening insn with equal LMUL

Resolves compiler internal error when RISC-V widening instructions have same source and destination register counts.

This commit fixes an internal compiler error (ICE) in the RISC-V backend related to widening vector instructions. The error occurred when the destination and source operands of a widening instruction used the same number of registers (nregs). The compiler’s riscv_v_widen_constraint_ok function had an incorrect assertion that nregs must be 1 in such cases. This patch modifies the function to return false instead of asserting when nregs is equal but greater than 1, preventing the ICE and allowing correct code generation for valid widening operations.

In Details

Fixes PR target/127269 by relaxing the assertion in riscv_v_widen_constraint_ok. The original assertion nregs == 1 was too strict when destination and source registers had the same count (nregs) for widening instructions. This could occur with operations like vwmul.vv where the source is derived from a wider vector register. The fix changes the check to return false (disallowing the overlap) when nregs > 1 and the counts are equal, rather than triggering an ICE.

For Context
RISC-V
An open standard instruction set architecture (ISA) based on Reduced Instruction Set Computing principles.
ICE
Internal Compiler Error, a condition where the compiler encounters an unexpected state and terminates instead of producing code.
widening instruction
A vector instruction that operates on data elements of one size and produces results with larger data elements, effectively widening the data.
LMUL
Lane multiplier in the RISC-V Vector extension, which determines the number of vector register elements that form a single vector register.
nregs
In the context of RISC-V vector instructions, this likely refers to the number of vector registers required to hold the entire vector operand.
RTL
Register Transfer Level, an intermediate representation used in GCC after the high-level language is parsed and transformed.
Filed Under: risc-vvectorcompiler bug