AArch64 vector permute optimization uses REV64+EXT.
AArch64 vector permute patterns can now be optimized into REV64 and EXT instructions, improving performance.
This commit introduces an optimization for the AArch64 architecture that recognizes specific vector permute patterns, such as those generated by __builtin_shuffle, and transforms them into a sequence of REV64 and EXT instructions. This new optimization can significantly improve performance by replacing a less efficient table-lookup (tbl) instruction with a more streamlined two-instruction sequence. The optimization is intelligently applied only when the pattern does not occur within a loop, preventing potential performance degradation in loop-heavy code.
In Details
The AArch64 Advanced SIMD (NEON) instruction set provides vector permute instructions. This change enhances the expander in aarch64_expand_vec_perm_const_1 within config/aarch64/aarch64.cc to identify specific constant vector permutations that can be efficiently implemented using REV64 (Reverse Bytes in Doubleword) followed by EXT (Extract). This pattern is particularly useful for operations like reversing byte order within lanes or achieving specific byte shuffling. A new helper function, aarch64_evpc_rev64_ext, is introduced to encapsulate this logic, and an additional check, `is_…
- AArch64
- The 64-bit ARM architecture, commonly used in mobile devices and servers.
- Advanced SIMD (NEON)
- ARM's SIMD (Single Instruction, Multiple Data) architecture extension that provides hardware acceleration for multimedia and signal processing applications by performing operations on multiple data points simultaneously.
- vector permute
- A vector operation that rearranges the elements within a vector according to a specified pattern or index list.
- __builtin_shuffle
- A GCC and Clang intrinsic function that performs a vector shuffle operation, rearranging elements from one or two source vectors into a destination vector based on a control mask.
- REV64
- An AArch64 NEON instruction that reverses the order of bytes within each 64-bit element of a vector register.
- EXT
- An AArch64 NEON instruction that extracts a portion of a vector register and places it into another vector register.
- tbl
- An AArch64 NEON instruction that performs a table lookup, rearranging elements of a vector based on indices provided in another vector.