aarch64: Use dot product for byte-to-word widening sum
Replaces multiple add operations with a single dot product for widening sums on aarch64, improving performance.
This change optimizes widening sum operations on aarch64 by utilizing the dot product instruction ([SU]DOT). Previously, summing bytes into 64-bit elements required multiple add operations. The new approach uses a single dot product instruction, which, while not reducing instruction count, better distributes the vector work and yields a performance improvement of up to 24% for unsigned char sums into long on compatible processors.
In Details
The aarch64_expand_reduc_widen_sum function has been updated to leverage the [SU]DOT instruction for the byte-to-word step in widening sum reductions. This specifically benefits the V2DI <- V16QI shape, replacing a chain of [SU]ADDLP and [SU]ADALP with a single [SU]DOT and a subsequent [SU]ADALP. The instruction count remains the same, but the vector work is spread more efficiently, leading to performance gains on architectures supporting dot product instructions.
- [SU]DOT
- An AArch64 SIMD instruction that performs a dot product operation. It multiplies corresponding elements in two vectors and sums the results, producing a single scalar value per destination element. This is useful for accumulating sums efficiently.
- [SU]ADDLP
- An AArch64 SIMD instruction that adds adjacent pairs of elements in a source vector and places the results in the next wider element size in the destination vector. It's used for widening sum operations.
- [SU]ADALP
- An AArch64 SIMD instruction similar to [SU]ADDLP, but it adds adjacent pairs of elements from two source vectors into the next wider element size in the destination vector. It's also used for widening sum operations.
- V2DI <- V16QI
- Represents a SIMD operation where 16 bytes (V16QI) are reduced to two 64-bit elements (V2DI) through a widening sum.