aarch64: Use SVE2 SQSHRNB and UQSHRNB for narrowing shifts.
AArch64 SVE2 now uses specialized instructions for saturating narrowing shifts, improving efficiency.
GCC’s AArch64 backend now leverages SVE2’s SQSHRNB and UQSHRNB instructions for saturating narrowing right shifts. This allows the compiler to fuse a constant right shift with a saturating truncation into a single instruction, where previously these were separate operations. The changes extend vector mode matching to cover relevant SVE modes and update machine description files to recognize these fused operations, improving performance for code involving saturating shifts and truncations on SVE2-capable hardware. This resolves PR126629.
In Details
The AArch64 SVE2 vectorizer has been enhanced to utilize SQSHRNB (Signed Saturating Doubling Horizontal Add and Narrow Round to nearest, with Bias) and UQSHRNB (Unsigned Saturating Doubling Horizontal Add and Narrow Round to nearest, with Bias) instructions. These instructions fuse a constant right shift with a saturating truncation. The changes in iterators.md add modes where element sizes halve without increasing lane count, and new patterns in aarch64-sve2.md (*aarch64_sve_<shrn_op>shrnb<mode>) match saturating truncations around arithmetic or logical right shifts by a constant v…
- SVE2
- Scalable Vector Extension 2. An extension to the ARMv8.2-A architecture, providing advanced vector processing capabilities beyond SVE, including new instructions for various operations.
- SQSHRNB / UQSHRNB
- SVE2 instructions that perform a saturating narrowing right shift. They combine a shift operation with a saturation to a smaller data type, improving efficiency for certain data processing tasks.
- Narrowing shift
- A shift operation that also reduces the size of the data elements, typically by a factor of two, often accompanied by saturation to prevent overflow or underflow.
- Vectorizer
- A component of the compiler that automatically transforms scalar code into vector (SIMD) code, leveraging specialized processor instructions to perform the same operation on multiple data elements simultaneously.