aarch64: Treat PREFETCH addresses like MEM addresses
Improves aarch64 code generation by ensuring PREFETCH instructions are handled similarly to memory accesses.
This commit enhances the combine pass on aarch64 to treat PREFETCH instruction addresses with the same simplification logic as MEM addresses. Previously, address computations rewritten by combine for MEM accesses were not applied to PREFETCH, causing issues with 32-bit indices. This fix ensures that address calculations, such as zero-extends on 32-bit values, are correctly preserved for PREFETCH, leading to more efficient code generation and saving dynamic instructions, particularly for functions like __builtin_prefetch.
In Details
The combine pass in GCC performs target-independent optimizations on RTX (register transfer language) expressions. On aarch64, combine_simplify_rtx uses make_compound_operation to simplify addresses. This commit extends this simplification to PREFETCH instructions, which, like MEM accesses, contain an address. Previously, a zero-extend operation used to cast a 32-bit index to a 64-bit address was not correctly propagated by combine for PREFETCH, requiring a separate address computation. This change unifies the handling, ensuring such address forms are recognized by target predic…
- combine pass
- A GCC optimization pass that performs target-independent simplification of RTX (Register Transfer Language) expressions. It aims to rewrite complex expressions into simpler forms suitable for further optimization or code generation.
- PREFETCH
- An instruction that hints to the processor to prefetch data into the cache, potentially improving performance by overlapping memory access latency with computation.
- MEM
- Represents a memory operand in GCC's intermediate representation (RTX). It refers to data stored in memory.
- aarch64
- The 64-bit ARM architecture instruction set. GCC supports generating code for this architecture.
- RTX
- Register Transfer Language, GCC's internal intermediate representation used to represent code before it is translated into machine code.
- zero extend
- An operation that expands a smaller integer value into a larger one by filling the new high-order bits with zeros. This is in contrast to sign extension, which fills with copies of the most significant bit.