i386: Relax register constraints for BT patterns
Allows more registers for bit test instructions on i386, potentially improving instruction scheduling.
This commit relaxes the register constraints for the bt (bit test) instruction patterns on the i386 architecture. By changing the constraint for the first operand from the more restrictive ‘q’ (general-purpose byte registers) to ‘r’ (any general-purpose register), the compiler can utilize a wider range of registers. This change aims to improve instruction scheduling flexibility and potentially performance.
In Details
The bt<mode> instruction pattern in i386.md previously used a "q" register constraint for operand 1, restricting it to legacy byte-addressable registers. This commit relaxes it to "r", allowing any general-purpose register. Additionally, the "r,m" constraints on operand 0 of the *bt<SWI48:mode>_mask pre-reload splitter were removed, keeping only the nonimmediate_operand predicate. These changes provide more flexibility in register allocation for bit test operations.
- bt instruction
- A x86 instruction that tests a specified bit in a specified source and sets the ZF flag accordingly. It can also optionally store the bit's value in a destination register.
- Register constraint
- In GCC's instruction patterns (MD files), a constraint specifies the type of operand (e.g., register, memory, immediate) that an instruction can accept. 'q' refers to specific byte registers, while 'r' refers to any general-purpose register.
- Pre-reload splitter
- A type of instruction pattern in GCC that is generated before the main register allocation (reload) phase to break down complex operations into simpler ones.