RISC-V: Fix register overlap for vs1 of widening integer reduction
Ensures vs1 does not overlap vs2 in RISC-V widening reductions.
This change fixes a register overlap issue in RISC-V widening integer reductions where the vs1 operand could fall within the vs2 register group. A new constraint, Wn3, is introduced to enforce that vs1 does not overlap with vs2, adhering to the RISC-V vector specification and preventing incorrect instruction generation.
In Details
These commits add test cases for register group overlap in RISC-V vector extension instructions, specifically vwredsum.vs and vwredsumu.vs. The tests target scenarios where the vs1 operand might incorrectly fall within the vs2 register group, which is forbidden by the RISC-V vector specification (Section 5.2). The fix involves adding a new constraint (Wn3) and associated logic in riscv-v.cc to prevent such overlaps during instruction selection.
- RISC-V vector extension
- An extension to the RISC-V instruction set architecture that adds support for single instruction, multiple data (SIMD) operations, allowing a single instruction to process multiple data elements in parallel.
- vwredsum.vs
- RISC-V vector instruction for widening signed integer reduction (summation).
.vsindicates that the destination register group is specified by thevdregister and the source register groups arevs1andvs2. - SEW
- Standard Element Width. Refers to the width of individual data elements within a vector register (e.g., 8-bit, 16-bit, 32-bit).
- EEW
- Effective Element Width. The width of the elements being processed by a vector operation, which can be different from the SEW, especially in widening operations.
- Register group
- A contiguous block of vector registers used by a single instruction. The size of the group depends on the operation's element width and the vector length.