Improve AArch64 rounding shift-right pair reachability.
Makes AArch64 rounding shift-right instructions more accessible to generic code.
AArch64’s rounding shift-right instructions were previously only reachable by their own specific expanders, preventing general code and the optimizer from utilizing them effectively. This change modifies these instructions to accept shift amounts as vectors, making them compatible with generic code and improving optimization opportunities, such as simplifying sequences involving addition and shifts.
In Details
This commit modifies the RTL patterns for AArch64's rounding shift-right instructions (aarch64_<sra_op>rshr_n<mode>_insn and aarch64_<sra_op>rsra_n<mode>_insn). Previously, they took a scalar shift amount, limiting their use. By accepting a vector shift amount, these patterns now align with the output of C code using widened operands, allowing the optimizer (combine) to recognize and fuse operations, such as SRSHR and SRSRA, more effectively. This affects SIMD and vector operations, particularly in widening contexts.
- RTL
- Register Transfer Language, an intermediate representation used by GCC between the front-end and back-end. It represents operations on registers.
- ACLE
- ARM C Language Extension, providing intrinsic functions for specific ARM architecture features.
- combine
- An optimization pass in GCC that performs instruction combination and simplification on RTL.
- V2XWIDE
- Refers to a vector data type that is twice the width of the source elements, used for intermediate calculations in SIMD operations.