Improve RISC-V conditional XOR sequences.
RISC-V code generation for conditional XOR with constants is improved, enabling branchless sequences.
This patch enhances RISC-V code generation for conditional XOR operations with constants, addressing an inefficiency identified in PR125731. By modifying the get_base_reg_or_constant function to handle constants and adjust mode handling, the compiler can now generate more efficient, branchless sequences for certain conditional XOR patterns, improving performance.
In Details
The if-converter's get_base_reg function previously returned NULL for constant operands, inhibiting noce_try_cond_arith from generating optimized conditional XOR sequences. This commit modifies get_base_reg to get_base_reg_or_constant to support constants. When constants are returned, the mode for the new pseudo-register is now derived from the other operand of the binary operation, enabling the if-converter to produce branchless code for conditional XORs.
- if-converter
- A compiler optimization pass that attempts to convert conditional control flow (like if-else statements) into branchless code, often using conditional move instructions or predicated execution.
- RISC-V
- An open-standard Instruction Set Architecture (ISA) based on Reduced Instruction Set Computer principles.
- branchless
- Code that avoids using conditional branch instructions, often leading to better performance on modern CPUs by preventing pipeline stalls.
- pseudo-register
- A temporary register used internally by the compiler during optimization and code generation, which may or may not map directly to a hardware register in the final output.
- VOIDmode
- A special mode in GCC representing a value that has no type or size, typically used for operations that don't produce a usable value.