SATURDAY, JULY 18, 2026
risc-v
RISC-V: Widen fusion pair bitmask to unsigned HOST_WIDE_INT
Increases the size of the fusion pair bitmask in RISC-V to support more instruction fusion types in the future.
The RISC-V compiler backend now uses a wider bitmask type for instruction fusion pairs. This change accommodates a larger number of potential fusion types, preventing overflow issues as more advanced CPU features are supported, and enabling future extensibility.
In Details
The riscv_fusion_pairs enum and riscv_tune_param::fusible_ops field were using unsigned int, which provided only 18 bits for fusion pair bitmasks. This commit widens these to HOST_WIDE_INT_1U to allow for more than 32 fusion pairs, which is critical for supporting future RISC-V microarchitectures with more complex instruction fusion capabilities.
For Context
- Instruction Fusion
- A compiler optimization where two or more independent instructions are combined into a single, more efficient instruction.
- HOST_WIDE_INT
- A data type in GCC that is guaranteed to be wide enough to hold any pointer or any scalar type on the host system.
- RISC-V
- An open-standard instruction set architecture (ISA) based on Reduced Instruction Set Computer principles.