RISC-V: Fix sibcall address legalization in MI thunks.
Corrects RISC-V subroutine call (sibcall) address handling in machine instruction thunks.
This commit addresses an issue in the RISC-V backend where the generation of machine instruction (MI) thunks could cause an assertion failure when legalizing sibcall addresses. The problem occurred because MI thunks were generating RTL as if register allocation was complete, leading to incorrect pseudo-register creation. The fix ensures the correct register (STATIC_CHAIN_REGNUM) is used for post-reload thunk code, resolving PR126449.
In Details
On RISC-V, sibcalls (small indirect calls) typically use a static chain register. MI thunks are generated post-reload and materialize call addresses. The previous logic incorrectly created a pseudo-register for sibcall addresses in this context, triggering a gen_reg_rtx assertion. This patch modifies riscv_legitimize_call_address to use STATIC_CHAIN_REGNUM for sibcalls materialized in post-reload thunks, aligning with the register usage for sibcalls expanded earlier.
- RISC-V
- An open-standard instruction-set architecture (ISA) based on Reduced Instruction Set Computer principles.
- sibcall
- A special type of subroutine call instruction designed for making short, indirect calls, often optimized for performance.
- MI thunk
- A small piece of generated code (thunk) created at the Machine Instruction (MI) level, often used to bridge different calling conventions or low-level code generation requirements.
- RTL
- Register Transfer Language, an intermediate representation used in GCC that describes operations at a lower level than GIMPLE, closer to machine code.
- legalization
- The process in a compiler's backend where intermediate representations are transformed to conform to the constraints and capabilities of the target machine's instruction set.