expand: Handle non-word addressable modes for vector registers.
Compiler can now handle non-word addressable modes for vector registers by spilling to memory or requiring target-specific move patterns.
The compiler’s expand pass now correctly handles non-word addressable modes for vector registers, crucial for targets like aarch64 and riscv where a vector register’s natural size might exceed the word size. It achieves this by spilling unsplittable modes to memory or by deferring to extract_bit_field. Additionally, targets are now required to provide integer move patterns for modes up to REGMODE_NATURAL_SIZE to avoid expansion progress issues.
In Details
The expand pass in GCC was extended to handle modes where REGMODE_NATURAL_SIZE exceeds UNITS_PER_WORD. Previously, it assumed modes could either be moved directly or split into words. This change modifies expmed.cc and lower-subreg.cc to spill unsplittable modes to memory or avoid decomposing registers if the mode's natural size is larger than a word. A new requirement in tm.texi mandates targets to supply appropriate integer move patterns to prevent infinite loops during expansion of subreg-punned registers.
- REGMODE_NATURAL_SIZE
- A target-specific macro indicating the natural size of a machine mode in bits. This is important for vector operations where a single vector register might hold multiple smaller data elements.
- UNITS_PER_WORD
- A target-specific macro defining the number of units (e.g., bytes) that constitute a machine word. This is fundamental for understanding data alignment and manipulation on a given architecture.
- subreg
- A machine mode representing a subset of bits within a larger register. This is used to access parts of a vector register or other larger data types stored in registers.
- move pattern
- A machine-description pattern that specifies how to move data between registers or memory. These patterns are essential for the compiler to generate efficient machine code for data transfer operations.