AArch64 SVE enables vector DImode high-part multiply.
Improves vectorizer capabilities on AArch64 by using SVE's UMULH/SMULH for 64x64 high-part multiplication.
This change enhances the AArch64 vectorizer by enabling it to perform vector DImode high-part multiplications using Scalable Vector Extension (SVE) instructions. Previously, Advanced SIMD lacked this capability, preventing optimization of loops requiring 64x64 high-part multiplies (e.g., calculating the upper 64 bits of a 128-bit product). By leveraging SVE’s UMULH and SMULH instructions on Z registers, GCC can now optimize these loops more effectively, generating more efficient machine code.
In Details
Extends the MUL_HIGHPART optab from SVE_I to SVE_I_SIMD_DI in aarch64-sve.md and aarch64-sve2.md. This allows the vectorizer to use SVE's UMULH and SMULH instructions for DImode operands, which are mapped to Z registers (%Z specifier). This provides the missing 64x64 high-part multiply functionality for Advanced SIMD, enabling optimization of loops previously unhandled.
- AArch64
- The 64-bit ARM architecture, commonly used in mobile devices and servers.
- SVE
- Scalable Vector Extension. An AArch64 feature that provides vector processing capabilities with variable vector lengths, allowing code to adapt to different hardware implementations.
- DImode
- A GCC internal machine mode representing a 64-bit integer type.
- high-part multiply
- A multiplication operation where only the most significant bits of the result are computed. For example, multiplying two 64-bit numbers to get the upper 64 bits of the 128-bit product.
- vectorizer
- A compiler component that attempts to transform scalar code into vector code, utilizing SIMD (Single Instruction, Multiple Data) instructions for parallel processing.
- Advanced SIMD
- ARM's implementation of SIMD instructions, also known as NEON. It provides 64-bit (D) and 128-bit (Q) registers for vector operations.