RISC-V: Improve slliw shifted bitfield split constraints
Refines constraints for RISC-V slliw instruction's bitfield split pattern to ensure correctness.
This commit refines the constraints for the split pattern of the RISC-V slliw instruction when dealing with shifted bitfields. It ensures the pattern only matches bitfields starting at bit 0 and that the upper bits of the operand correctly reflect the sign-extended result of the slliw operation.
In Details
This commit corrects the constraints in the config/riscv/riscv.md for the slliw instruction's bitfield split pattern. It restricts the split to match only bitfields starting at bit 0 and enforces that the most significant bits of the result accurately represent the sign-extended output of slliw, addressing potential theoretical issues related to operand alignment and sign extension.
- slliw
- A RISC-V instruction that performs a signed left word immediate shift, shifting a 32-bit word by an immediate value.
- Bitfield split
- A compiler technique to extract or manipulate specific ranges of bits (bitfields) within a larger data word, often involving multiple instructions.
- Constraints
- Rules in GCC's machine description files that specify which operands or patterns are valid for a given instruction, ensuring correct code generation.
- Sign extension
- The process of extending the sign bit of a number to preserve its value when converting to a larger data type.