MONDAY, AUGUST 31, 2026
risc-v
RISC-V: Set REGMODE_NATURAL_SIZE for VLS vectors
Ensures correct handling of sub-register access for RISC-V VLS vectors.
This commit adjusts the REGMODE_NATURAL_SIZE definition for RISC-V VLS (Vector Length Selectable) vector modes. It now correctly reports the size of a full vector, preventing invalid sub-register accesses and ensuring that operations on vector elements are properly managed.
In Details
Following recent middle-end changes, this patch sets REGMODE_NATURAL_SIZE for RISC-V VLS vector modes to reflect the full vector size. This change invalidates the previous practice of using subregister access (subregging) to manipulate individual vector elements. The plan is to address resulting code-quality regressions by modifying vec-vec extracts/sets and potentially adding new RTL codes.
For Context
- REGMODE_NATURAL_SIZE
- A compiler internal macro that defines the native size of a register mode. In this context, changing it to 'one vector' signifies that sub-register access within a vector register is no longer permitted.
- VLS
- Vector Length Selectable, a feature of the RISC-V Vector Extension that allows vector registers to hold different numbers of elements depending on the vector length set at runtime.
- subregister
- A part of a larger hardware register. In compiler terminology, it refers to accessing a portion of a register as if it were a separate entity.
- RTL
- Register Transfer Language, an intermediate representation used by GCC to represent the program's structure and operations before machine code generation.
- PR middle-end/125390
- A reference to a specific bug report or problem report within the GCC bug tracking system, related to the middle-end of the compiler.