RISC-V: Allow register overlap for widened float vector instructions
RISC-V vector instructions now allow register overlap for widened float operations.
The RISC-V vector extension (RVV) now permits register overlap for dual-widening floating-point instructions, including vfwadd.vv, vfwsub.vv, and vfwmul.vv. This change is accompanied by new test cases in the testsuite to verify correct handling of register group overlaps for various floating-point types and vector mask configurations.
In Details
This change modifies the vector instruction emission for RISC-V, specifically targeting the vfwadd.vv, vfwsub.vv, and vfwmul.vv instructions. The vector.md file is updated to use the Wvr constraint, enabling register overlap similar to that already supported by vw{add,sub,mul}[u].vv. New test cases are added to the gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/ directory to validate register group overlap behavior across different data types (f16, f32) and vector mask configurations (m1, m2, m4, mf2, mf4).